The present disclosure relates generally to testing a circuit design, and more specifically to testing such circuit using a programmable emulation tool having improved performance.
Integrated circuit (IC) designers commonly describe their designs in hardware description language (HDL) such as Verilog, VHDL, SystemC, and the like. In IC design, hardware emulation may refer to the process of replicating behavior of one or more pieces of hardware, hereinafter also referred to as a design under test (DUT), with another piece of hardware, such as a special-purpose emulation system. An emulation model is usually generated in accordance with a hardware description language source code representing the design under test. The emulation model is compiled into a format used to program the emulation system. Running the emulation system that has been programmed enables debugging and functional verification of the design under test. Overall progress of the emulation is usually controlled by a master clock signal generated on the emulator hardware.
With recent advances in technology, circuit designs are becoming more and more complex. Therefore, there is a need in the art for improving performance of hardware emulation systems, reducing overhead while mapping the design to programmable hardware in the emulation systems, and reducing verification time.